With 8 years of experience in digital design at Xilinx, I’m an experienced FPGA developer.
My experience includes a variety of highly-parameterized VHDL and Verilog designs, optimized for the Xilinx architecture.
I also have experience in video and image processing, and interfacing hardware modules to a microprocessor.

I’m available for contract work for FPGA designs.

Email me at jamesogden@gmail.com if you’d like to know if I’m a fit for your project.

More specifically, my experience at Xilinx is as follows:

Development Engineer at Xilinx

(Public Company; 1001-5000 employees; XLNX; Semiconductors industry)

July 2000 � March 2008 (7 years 9 months)

FPGA Design, CoreGen Integration, VHDL/Verilog.
* Lead designer/developer CoreGen Block Memory Generator Core v1.0 to v2.4 (Project Lead)
* Lead designer/developer CoreGen FIFO Generator Coregen Core v1.0 to v4.1 (Project Lead)
* Lead designer/developer CoreGen Content Addressable Memory Core v1.0 to v5.0 (Project Lead)
* Co-designer/developer CoreGen 8b/10b Encoder & 8b/10b Decoder Coregen Cores
* Created optimized designs which maximize the capabilities of Xilinx FPGAs
* Contributed to 3 Xilinx Invention Disclosures submitted for Patent Review, 1 Patent Issued
* Contributed to process improvements including group-standard computer environments and collaborative web-based documentation and project management.
* Contributed to improvements in Xilinx hardware and software through collaboration with IC design, Coregen, and XST design teams.
* Supported Field Application Engineers and customers on issues related to these cores